In digital transmission systems it is often required to align an incoming data signal to a new reference clock signal. Typically, the incoming data signal is aligned to a first reference clock signal and an outgoing data signal is aligned to the new reference clock signal. The first and new reference clock signals, although usually being at the same nominal rate, tend to vary with respect to each other. They exhibit characteristics such as wander, jitter, phase differences and the like. Elastic store arrangements have typically been employed to minimize the effects of these characteristics. These elastic store arrangements required some mechanism to prevent underflow and overflow of the data. To this end, the separation between the elastic store write address and read address was obtained by employing a phase detector and used to control the rate at which the data was read out of the elastic store. Such a mechanism is commonly known as stuffing.
In some digital transmission systems, however, there are so-called "gaps" in the incoming data signal. That is, there are portions of the incoming data signal that do not include information which is to be passed through the elastic store. Examples of such digital transmission signals are the DS3 digital signal, DS1 digital signal, SONET STS1 signal, SONET VT signal and the like.
In a typical elastic store arrangement, the write address is incremented after each element of the incoming data signal has been written. However, when one or more gaps appear in the incoming data signal, incrementing of a write address counter is inhibited for the one or more gap interval(s). This inhibiting of the write address counter can cause apparent "jumps" in the separation between the elastic store write address and read address which, in turn, causes undesirable stuffing. The technique usually employed to eliminate the write-read address separation jump problem involves the use of a first elastic store and associated phase detector to smooth out the gaps in the incoming data signal and to appropriately adjust the first reference clock signal. The smooth data and an adjusted first reference clock signal are then supplied to a second synchronizing elastic store and associated phase detector which yields the desired data signal that is synchronized to the new reference clock signal. Although the use of the additional elastic store and phase detector solves the problem, such a solution is undesirable because it is expensive to implement. Additionally, use of the additional smoothing elastic store introduced unnecessary time delay through the smoothing process.